1. Field of the Invention
The present invention relates to a semiconductor device having a multiple-wiring-layer structure and a method for manufacturing the same.
2. Description of Related Art
In a semiconductor device having a multiple-wiring-layer structure, insulation between wiring layers is provided by interlayer dielectric films. Techniques for forming interlayer dielectric films are described in, for example, Japanese Laid-open patent applications HEI 7-86284 and HEI 7-161703.
These interlayer dielectric films disclosed in the above references have internal compression stress. This results in warping of a semiconductor wafer when semiconductor devices are manufactured. The warping of the semiconductor wafer creates various problems in manufacturing of semiconductor devices. For example, a semiconductor wafer is mounted on a vacuum chuck while thin films (interlayer dielectric films, metal wiring layers, etc.) are formed. If the semiconductor wafer is warped, heat is not uniformly conducted through the semiconductor wafer. As a result, the thickness of the thin film thus formed is not uniform. In many occasions, many interlayer dielectric films are formed in between the wiring layers. As a result, more wiring layers result in a greater number of interlayer dielectric films. As a consequence, the compression stress in the semiconductor wafer increases, with the result that the warping of the semiconductor wafer becomes greater.
It is an object of the present invention to provide a semiconductor device having a structure that is capable of reducing warping of a semiconductor wafer when the semiconductor device is manufactured. It is also an object of the present invention to provide a method for manufacturing the same.
In accordance with one embodiment of the present invention, a semiconductor device has a semiconductor substrate having a main surface, at least one wiring layer formed over the main surface, and interlayer dielectric films formed over the at least one wiring layer or between the main surface and the at least one wiring layer. At least one of the interlayer dielectric films includes a first film having an internal tensile stress, and at least another of the interlayer dielectric films includes a second film having an internal compression stress.
In accordance with one embodiment of the present invention, the semiconductor device is manufactured by a method comprising at least the steps of: (a) forming the first film having an internal tensile stress by reacting a silicon compound with hydrogen peroxide by a CVD method; and (b) forming the second film having an internal compression stress by a CVD method.
In accordance with one embodiment of the present invention, in step (a), the first film is a silicon oxide film. When the silicon oxide film is formed by reacting a silicon compound with hydrogen peroxide by a CVD method, the film has an internal tensile stress. On the other hand, in step (b), the second film formed by a CVD method is a silicon oxide film having an internal compression stress. As a result, the tensile stress and the compression stress in the interlayer dielectric films act on the semiconductor wafer when the semiconductor device is manufactured. Accordingly, an overall stress that acts on the semiconductor wafer becomes small or zero (0). Therefore, warping of the semiconductor wafer is reduced or eliminated when the semiconductor device is manufactured. It is noted that step (a) and step (b) can be performed in any order. In other words, step (a) can be performed first, or step (b) can be performed first.
CVD methods that cause internal compression stresses in a formed film include, for example, pyrolysis or hydrolysis of organic oxysilane, and plasma CVD method or reduced pressure CVD method that utilizes oxidation of silane.
After step (b), the interlayer dielectric film including the second silicon oxide film may preferably be polished by chemical-mechanical polishing (CMP). As a result, the interlayer dielectric film including the second silicon oxide film is planarized.
A through hole may be formed in the interlayer dielectric film including the second silicon oxide film. A high melting point metal, such as tungsten, may preferably be used as a conductive layer to fill in the through hole formed in the interlayer dielectric film including the second silicon oxide film.
In step (a), the first silicon oxide film may be formed by reacting a silicon compound and hydrogen peroxide utilizing a CVD method. As a result, the formed layer has an excellent planarization characteristic. More specifically, the first silicon oxide film formed in step (a) has a high flowability itself and a high self-planarization characteristic. This phenomenon is believed to take place due to the following mechanism. When a silicon compound and hydrogen peroxide are reacted by the CVD method, silanol is formed in vapor phase, and the silanol deposits on the surface of the wafer to provide a film having a high flowability.
For example, when monosilane is used as a silicon compound, silanol is formed by reactions defined by formulae (1) and (1)xe2x80x2 as follows:
Formula (1)
SiH4+2H2O2xe2x86x92Si(OH)4+2H2 
Formula (1)xe2x80x2
SiH4+3H2O2xe2x86x92Si(OH)4+2H2O+H2 
Silanol formed by the reactions defined by Formulae (1) and (1)xe2x80x2 becomes silicon oxide as a result of disconnection of water by polycondensation reaction defined by Formula (2) as follows:
Formula (2)
Si(OH)4xe2x86x92SiO2+2H2O 
The silicon compounds include, for example, inorganic silane compounds, such as monosilane, disilane, SiH2Cl2, SiF4 and the like, and organo silane compounds, such as CH3SiH3, tripropyle-silane, tetraethylorthosilicate and the like.
The film formation in step (a) described above may preferably be conducted by a reduced pressure CVD method at temperatures of about 0-20xc2x0 C. when the silicon compound is an inorganic silicon compound, and at temperatures of about 0-150xc2x0 C. when the silicon compound is an organic silicon compound. If the temperature during the film-forming step is higher than the upper limit of the above-described temperature ranges, the polycondensation reaction defined by Formula (2) progresses excessively. As a result, the flowability of the first silicon oxide film lowers and therefore it is difficult to obtain good planarization. On the other hand, if the temperature is lower than the lower limit of the above-described temperature ranges, the control of a film forming apparatus becomes difficult. For example, adsorption of cracked water content occurs within the chamber and dew condensation occurs outside the chamber.
The first silicon oxide film formed in step (a) may preferably be formed with a thickness that sufficiently covers step differences of the underlying layer. The minimum thickness of the first silicon oxide film depends on the height of protrusions and recesses of the underlying layer, and is preferably between about 300 and about 1000 nm. If the film thickness of the first silicon oxide film exceeds over the above-described upper limit, cracks may occur due to stresses of the film itself.
The interlayer dielectric film in accordance with embodiments of the present invention may have a single layered structure or a multiple layered structure. In the case of a multiple layered structure having multiple interlayer dielectric films, one of the interlayer dielectric films may have an internal compression stress and another of the layers may have an internal tensile stress. As a result, the interlayer dielectric films in the multiple layered structure as a whole may have an internal tensile stress or an internal compression stress.
In accordance with another embodiment of the present invention, a semiconductor device comprises a semiconductor substrate having a main surface, a plurality of wiring layers over the main surface, and interlayer dielectric films formed between the main surface and the plurality of wiring layers and between the wiring layers. At least one of the interlayer dielectric films includes a first silicon oxide film being formed by reacting a silicon compound with hydrogen peroxide through polycondensation reaction and having an internal tensile stress. At least another of the interlayer dielectric films includes a second silicon oxide film having an internal compression stress.
It is noted that the interlayer dielectric films having an internal compression stress are intended to merely provide a semiconductor device structure with an internal compression stress. Accordingly, another insulation film having an internal compression stress may be used to provide an internal compression stress, instead of the second silicon oxide film.
In a method for manufacturing a semiconductor device in accordance with one embodiment of the present invention, the step of forming the interlayer dielectric film including the first silicon oxide film includes, before step (a), step (c) of reacting a silicon compound with at least one of oxygen and a compound including oxygen through a CVD method to form a third silicon oxide film that serves as a base layer.
In step (c), the third silicon oxide film, that serves as a base layer, is formed by reacting a silicon compound with at least one of oxygen and a compound including oxygen by a CVD method. The base layer has a passivation function that prevents migration of water and excess impurities from the first silicon oxide film to an underlying layer below the base layer (a main surface of a semiconductor substrate when there is no underlying layer). Also, the base layer has a function to increase the cohesiveness between the first silicon oxide film and an underlying layer below the base layer (a main surface of a semiconductor substrate when there is no underlying layer).
In accordance with one embodiment of the present invention, a tapered through hole is formed in the interlayer dielectric film including the first silicon oxide film. In a preferred embodiment, the tapered through hole has aperture diameters that gradually reduce from an upper end section to a bottom section of the through hole.
Preferably, the etching speed for the first silicon oxide film is slightly greater than the etching speed for the third silicon oxide film that forms a base layer. As a result, the through hole has an adequate linear taper wall. An aluminum film or an aluminum alloy film can be filled in such a tapered through hole by sputtering, for example. As a result, a contact structure with an excellent conductivity is formed.
The through hole may be formed by an anisotropic dry etching. Also, a tapered through hole having an upper end section with a curved surface may be formed by a combination of an isotropic wet etching and an anisotropic dry etching.
A first aluminum film composed of aluminum or an alloy containing aluminum as a main component may be preferably formed in the through hole at temperatures of about 200xc2x0 C. or lower. Then, a second aluminum film composed of aluminum or an alloy containing aluminum as a main component may preferably be formed at temperatures of about 300xc2x0 C. or higher.
The alloy containing aluminum as a main component may be a two-component or a three-component alloy containing at least one selected from copper, silicon, germanium, magnesium, cobalt and beryllium.
When a gettering effect is required to get alkali-ions, an impurity such as for example phosphorous in the amount of about 1-6 weight % may be added to the third silicon oxide film that forms the base layer. Alternatively, for example, a PSG film containing phosphorous in the amount of about 1-6 weight % may be formed between the third silicon oxide film and the first silicon oxide film.
In accordance with one embodiment of the present invention, a semiconductor device manufactured by the manufacturing method described above comprises a semiconductor substrate having a main surface, a plurality of wiring layers over the main surface, and interlayer dielectric films formed between the main surface and the plurality of wiring layers and/or between adjacent ones of the wiring layers. At least one of the interlayer dielectric films includes a third silicon oxide film that serves as a base layer, and a first silicon oxide film above the third silicon oxide film. The first silicon oxide film is formed by reacting a silicon compound with hydrogen peroxide through a polycondensation reaction and has an internal tensile stress. Also, at least another of the interlayer dielectric films includes a second silicon oxide film having an internal compression stress.
In a preferred embodiment, the step of forming the interlayer dielectric film including the first silicon oxide film may preferably include, after step (a), step (d) of forming a fourth porous silicon oxide film by reacting a silicon compound with oxygen or a compound containing oxygen.
In step (d), a silicon compound is reacted with at least one of oxygen and a compound containing oxygen by a CVD method to form a fourth porous silicon oxide film over the first silicon oxide film. The fourth silicon oxide film functions as a cap layer. An impurity such as, for example, phosphorous, boron or the like may preferably be added to the fourth silicon oxide film. More preferably, phosphorous is added to the fourth silicon oxide film. As a result, in addition to its porous structure, the film can relieve stresses by weakening the molecular bonding force between Si and O molecules of the silicon oxide that forms the film. In other words, the layer is moderately soft but hard enough to resist to cracks. One important role of the fourth silicon oxide film is a function in which the impurity such as phosphorous contained in the silicon oxide film functions as a getter of mobile ions, such as alkali-ions that have deteriorating effects on the device element-reliability characteristics. The impurity concentration of the impurity contained in the fourth silicon oxide film may preferably be about 1-6 wt %, in consideration of the gettering function and the stress relieving function of the film.
Also, the fourth silicon oxide film has a compression stress of about 100-600 MPa, and therefore functions to prevent the generation of cracks due to an increased tensile stress that is caused in the first silicon oxide film when it undergoes polycondensation reaction. Further, the fourth silicon oxide film functions to prevent the first silicon oxide film from absorbing moisture.
Step (d) may preferably be conducted by a plasma CVD method with a high frequency at temperatures of about 300-450xc2x0 C. This step is effective in disconnecting water content from the first silicon oxide film 42.
The compound including oxygen that is used in step (d) may preferably be nitrogen monoxide (N2O). By the use of nitrogen monoxide as a reactant gas, the nitrogen monoxide in a plasma form likely reacts with the hydrogen bond (xe2x80x94H) of the silicon compound that forms the first silicon oxide film. As a result, disconnection of gasification components (hydrogen, water) from the first silicon oxide film is promoted even while the fourth silicon oxide film is being formed.
Alternatively, a normal pressure CVD method at temperatures of about 300-550xc2x0 C. may be conducted, instead of the plasma CVD method in step (d). In this case, ozone may preferably be used in step (d) as a compound including oxygen.
Also, before the fourth silicon oxide film is formed in step (d), the first silicon oxide film may preferably be exposed to an ozone atmosphere. Since ozone likely reacts with hydrogen bond (xe2x80x94H) and hydroxyl (xe2x80x94OH) of the silicon compound that forms the first silicon oxide film, disconnection of hydrogen and water from the first silicon oxide film is promoted.
The thickness of the fourth silicon oxide film is preferably about 100 nm or greater in consideration of the planarization and prevention of cracks.
A tapered through hole may be formed in the interlayer dielectric films including the first silicon oxide film and the fourth silicon oxide film. In a preferred embodiment, the tapered through hole has aperture diameters that gradually reduce from an upper end section to a bottom section of the through hole. The etching speed for the first silicon oxide film is slightly slower than the etching speed for the fourth silicon oxide film, and the first silicon oxide film and the fourth silicon oxide film are bonded to each other well at their boundary. As a result, the through hole has an adequate linear taper wall without step differences at the boundary between the first silicon oxide film and the fourth silicon oxide film. An aluminum film or an aluminum alloy film can be filled in such a tapered through hole by sputtering, for example. As a result, a contact structure with an excellent conductivity is formed.
The through hole described above may be formed by an anisotropic dry etching. Also, a tapered through hole having an upper end section with a curved surface may be formed by a combination of an isotropic wet etching and an anisotropic dry etching.
Further, a first aluminum film composed of aluminum or an alloy containing aluminum as a main component may preferably be formed in the above-described through hole at temperatures of 200xc2x0 C. or lower. Then, a second aluminum film composed of aluminum or an alloy containing aluminum as a main component may preferably be formed at temperatures of about 300xc2x0 C. or higher.
The alloy containing aluminum as a main component may be a two-component or a three-component alloy containing at least one selected from copper, silicon, germanium, magnesium, cobalt and beryllium.
In accordance with one embodiment of the present invention, a semiconductor device manufactured by the manufacturing method described above comprises a semiconductor substrate having a main surface, a plurality of wiring layers over the main surface, and interlayer dielectric films formed between the main surface and the plurality of wiring layers and between the wiring layers. At least one of the interlayer dielectric films includes a first silicon oxide film being formed by reacting a silicon compound with hydrogen peroxide through polycondensation reaction and having an internal tensile stress, and a fourth silicon oxide film that functions as a cap layer formed over the first silicon oxide film. At least another of the interlayer dielectric films includes a second silicon oxide film having an internal compression stress.
In accordance with one embodiment of the present invention, a method for manufacturing a semiconductor device may preferably further include the following steps after the interlayer dielectric film including the first silicon oxide film is formed: (e) forming a first through hole in the interlayer dielectric film including the first silicon oxide film; (f) forming a barrier layer, that defines a part of the wiring layers, on a surface of the first through hole and on a surface of the interlayer dielectric film; and (g) forming a conductive film, that defines a part of the wiring layers, on a surface of the barrier layer. As a result, the interlayer dielectric film including the first silicon oxide film has a portion defining the first through hole. As a result, the semiconductor device includes the barrier layer, that defines a part of the wiring layers, on surfaces of the first through hole and the interlayer dielectric film, and the conductive film, that defines a part of the wiring layers, on a surface of the barrier layer.
The first through hole may preferably be filled with a conductive film composed of aluminum or an alloy containing aluminum as a main component. Also, a second through hole may preferably be formed in the interlayer dielectric film having an internal compression stress. The second through hole may preferably be filled with a conductive film composed of a high melting point metal or an alloy containing a high melting point metal as a main component.
Other features and advantages of the invention will be apparent from the following detailed description, taken in conjunction with the accompanying drawings which illustrate, by way of example, various features of embodiments of the invention.